The present invention relates to the use of thin-film deposition technology to create high density interconnects on a laminated printed wiring board substrate. More specifically, the present invention pertains to a method for controlling the wall profile of vias and other features in the deposited thin-film layers to improve electrical and/or mechanical performance. The method of the present invention is useful for high density integrated circuit packaging of single chip, multi-chip, and support components such as resistors and capacitors. The method of the present invention is also useful for creating interconnections on high density daughter boards that carry packaged devices as well as in the semiconductor devices themselves.
The semiconductor industry continues to produce integrated circuits of increasing complexity and increasing density. The increased complexity of some of these integrated circuits has in turn resulted in an increased number of input/output pads on the circuit chips. At the same time, the increased density of the chips has driven the input/output pad pitch downward. The combination of these two trends has been a significant increase in the connector pin wiring density needed to connect the chips to packages that interface with the outside world and interconnect the chips to other integrated circuit devices.
A number of different technologies have been developed to interconnect multiple integrated circuits and related components. One such technology, based on traditional printed wiring board (xe2x80x9cPWBxe2x80x9d) technology that found wide use during the period in which integrated circuits were packaged in surface mount devices like quad flat packs (QFPs), is often referred to as multi-chip module laminate (xe2x80x9cMCM-Lxe2x80x9d) technology. MCM-L technology typically uses layers of copper foil and insulating dielectric material, typically as a sub-laminate sheet of a dielectric layer sandwiched between sheets of copper foil, as building blocks to create the required interconnect structures. The process of forming a conductive pattern on the sub-laminate in MCM-L technology typically includes forming a film of photo resist over a copper layer, patterning and developing the photo resist to form an appropriate mask, and selectively etching away the unwanted copper to leave a conductive pattern.
Interconnection between stacked layers can be provided by a plated through hole (xe2x80x9cPTHxe2x80x9d) formed by drilling a hole through the laminated stack and plating the inside surface of the hole. The drilling process is relatively slow and expensive and uses a relatively large amount of board space. As the number of interconnect pads increase, the amount of board area consumed by PTHs increases, reducing the area available for signal line routing. Additionally layers can be added to the laminate to accommodate additional wiring lines, but this typically increases the cost and decreases the electrical performance.
Substrates used in MCM-L technology can be efficiently manufactured in large area panels that lower the cost of production. Interconnect solutions using this technology generally have relatively good performance characteristics for components with sufficiently large pad spacing and low pad density because of conductivity of the relatively thick copper and low dielectric constant (e.g. less than or equal to 4.0) of the dielectric material. The printed wiring board industry; however has tried to keep pace with the advances in semiconductor manufacturing in terms of pad spacing and density. As a result, alternative technologies have been developed.
One approach to accommodate high-density pad components on an MCM substrate is to use thick film (screen printing) conductor traces on ceramic substrates (xe2x80x9cMCM-Cxe2x80x9d). Basically, MCM-C technology involves rolling a ceramic mix into, sheets, drying the sheets, punching vias, screening the rolled sheets with a metal paste to fill the vias and define the trace pattern on the surface of the ceramic, stacking and laminating all the layers together, then co-firing at a high temperature (e.g. greater than 850xc2x0 C.) to achieve the desired interconnections.
MCM-C construction has found extensive use in high density and high reliability products where the robustness of the high density interconnect package outweighs the cost considerations. The ability to create a hermetic seal,in the ceramic improves the ability to withstand environments not tolerable to conventional printed wiring board technology. While this technology is capable of high density packaging applications (e.g. greater than 1000 pads), it is also very costly. Additionally, performance characteristics, such as signal propagation time, are affected due to the relatively high dielectric constant (e.g. between 5.0 and 9.0) of the ceramic material.
To improve the interconnect density of MCM-L technology, an approach called build-up multi-layer has been developed. In this technology, a build-up layer is formed on one or both surfaces of a laminated wiring board core with patterned conductive layers and PTHs. There are many variations to this approach, but typically a dielectric layer approximately 50 microns thick is formed on both the top and bottom major surfaces of the conventionally fabricated printed wiring board substrate. Vias are made-in the conventional build-up layer by laser ablation, photo mask/plasma etch, or other known methods. An electroless seeding step is then done prior to a panel plating step that metalizes both the upper and lower surfaces. Subsequent masking and wet etching steps then define a desired conductive pattern over the build-up dielectric layers.
A third approach to forming high density wiring substrates uses thin-film type deposition and patterning technology. This technology is sometimes referred to as xe2x80x9cMCM-Dxe2x80x9d or deposition on laminate (xe2x80x9cDONLxe2x80x9d). This technology has been adapted to substrates of 40 centimeters by 40 centimeters or more, thereby providing efficiencies that lower the costs of production. MCM-D technology can be used on low cost printed wiring board structures, with or without a build-up layer on the printed wiring board. This combination of existing conventional high volume printed wiring board technology and advanced thin-film deposition technology represents a significant economic advantage and density improvement as compared to the previously discussed MCM-L and MCM-C technologies.
However, despite the definite advantages of MCM-D technology, there are potential problems that may result in failure modes and performance limitations if the deposited thin-film layers- are not properly implemented. One key to proper implementation of the deposited thin-film layers is reliably making the conductive vias between layers of patterned conductive traces. In MCM-L technology, the drilled holes are relatively large, and the plating solution reliably plates the inside diameter. In MCM-C technology, the thick-film paste is also somewhat liquid, and reliably fills the via holes to form a conductive via. However, in MCM-D technology, a combination of thin metal layers, relatively thick dielectric layers, small via geometry can reduce the reliability of conductive vias, or result in open vias and a rejected substrate.
One approach to improve conductive vias in MCM-D substrates is to re-flow or otherwise thermally alter the dielectric layer after forming the via holes. The via holes are typically formed in a layer of photo-sensitive polymer material that will become the dielectric layer underlying the thin-film metal layer. The dielectric precursor material is typically applied as a liquid, by spraying, spinning, dipping, etc., and pre-baked to convert the material to an essentially solid photosensitive layer. This pie-baked layer is then exposed to light through a patterned photo mask and developed. Development typically consists of washing the exposed.layer with a solvent or other liquid to remove part of the layer. The material exposed to the light might remain or might be washed away, relative to the un-exposed material, depending on whether the dielectric material is photo. positive or negative, similar to photo-resist materials.
After development, the dielectric material is typically hard-baked to produce the patterned dielectric layer. This pattern typically includes via holes. The sidewall profile of the hole can affect the subsequent reliability of the metal layer formed over the surface of the via. For example, if the bottom of the hole is larger than the opening, or even if the via hole walls are vertical, the opening can xe2x80x9cshadowxe2x80x9d portions of the via during a metal sputtering process, for example. This can form thin regions in the metal layer, affecting reliability.
One approach to avoiding this problem is to form sloped via walls by thermally treating the dielectric layer after development to re-flow the material. Other methods include the use of low photo-contrast dielectrics to achieve a less precise transition between developed and un-developed material, or using a photo resist/reflow/dry transfer method. These methods can form a via hole with a sloped wall; however, they are omni-directional, consume additional surface area otherwise desirable for signal line routing, and wall contour control remains difficult due to lack of accurate process control.
Accordingly; improved methods are desirable to control the side wall profile of the via walls in MCM-D technology.
The present invention provides a method of forming vias with sloped walls and improved metal layer formation in thin-film layers of high density interconnect substrates. Optical proximity effects are used to expose an edge region of a via or other feature in a photosensitive dielectric layer. In a further embodiment, an elongated via hole is formed, with sloped walls at each end of the long axis, thus conserving board area.
According to a method of the present invention, a mask used to define via locations is constructed in such a way that the.energy impinging on the dielectric defines both the shape of the via and the angle of the via walls in the thin-film dielectric layer. By controlling the shape of the via it is possible to achieve maximum interconnect wiring density and by controlling the angle of the via walls, it is possible to achieve reliable electrical contacts between metal layers.